1. Field of the Invention
The present invention relates to an analog to digital (A/D) conversion device for converting an analog input signal into numerical data using a pulse delay circuit that has a plurality of delay units connected in series with one another, each of the delay units inputs, delays, and outputs a pulse signal.
2. Description of the Related Art
As shown in FIG. 5A, a pulse delay type A/D conversion device 500 has been known, which has a pulse delay circuit 100, a clock generator 110, “m” pulse position numerizing units 120, and an adder 14. Such a pulse delay type A/D conversion device was disclosed in a Japanese patent laid open publication number JP 2004-7385, for example. In the conventional pulse delay type A/D conversion device 500, the pulse delay circuit 100 includes a plurality of delay units 102, each delay unit 102 inputting, delaying, and outputting a pulse signal, which are connected in series with one another. The clock generator 110 generates “m” sampling clocks CK1 to CKm, of different phases with one another. The “m” pulse position numerizing units 120 detects the number of the delay units 102 through which the pulse signal PA has passed through the pulse delay circuit 100 during one period that is determined based on both a reference clock CK0 and one of the sampling clocks CK1 to CKm generated by the clock generator 110. The “m” pulse position numerizing units 120 then outputs numerical data DT1 to DTm of n bits as the detection result. The adder 14 adds the “m” numerical data DT1 to DTm of n bits output from each of the “m” pulse position numerizing units 120, and then provides numerical data DΔT of “n+log2 m bits”.
In the A/D conversion device 500, each delay unit 102 forming the pulse delay circuit 100 is composed of a gate circuit such as an inverter, and an analogue input signal (voltage) Vin that becomes as a target for a A/D conversion to be processed is provided to each delay unit 102. The delay time of each delay unit 102 is changed according to the signal level (voltage level) of the analogue input signal Vin and is decreased according to the increasing of the analogue input signal Vin.
When the pulse signal PA is input to and transferred through the pulse delay circuit 100, the numerical data DT1 to DTm generated in synchronization with the analogue clock CK1 to CKm in each pulse position numerizing unit 120 is changed according to the signal level of the analogue input signal Vin. The signal level of the analogue input signal Vin is increased according to the increase of the numerical data DT1 to DTm. That is, each pulse position numerizing unit 120 performs the A/D conversion of the analogue input signal Vin, generates, and outputs the numerical data.
As shown in FIG. 6, a period of the reference clock CK0 is set to a constant time length Ts that is adequately longer than the delay time of each delay unit 102 (for example, more than several ten times of the delay time of each delay unit 102). The number of the stages for the delay units 102 in the pulse delay circuit 100 is set to the number that is adequately longer than the period Ts of the reference clock CK0 so that each pulse position numerizing unit 120 can perform the numerizing process more than a given times in synchronization with the reference clock CK0.
Each sampling clock CK1 to CKm is generated by delaying the reference clock CK0 and the phase of each sampling clock CK1 to CKm is delayed by unit time ΔT (=Td/m) which is obtained by dividing the delay time Td of the delay unit 102 forming the pulse delay circuit 100 by the number “m” of the sampling clocks CK1 to CKm. That is, each of the sampling clocks CK2 to CKm is delayed integral times of unit time ΔT such as 1×ΔT, 2×ΔT, 3×ΔT, . . . , and (m−1)×ΔT on the basis of the sampling clock CK1.
Each pulse position numerizing unit 120 performs the numerizing process of the number of the delay units 102 in the pulse delay circuit 100 through which the pulse signal PA passes during the sampling period (Ts+ΔT, Ts+2×ΔT, Ts+3×ΔT, . . . , and Ts+(m−1)×ΔT), and outputs the result of the numerizing to the adder 14. The sampling period (Ts+ΔT, Ts+2×ΔT, Ts+3×ΔT, . . . , and Ts+(m−1)×ΔT) is a time until a rising edge (or falling edge) of each sampling clock (CK1 to CKm) after the elapse of the period TS counted from a common initiation timing t0 for initiating the numerization process that is a rising edge (or a falling edge) of the sampling clock signal CK1.
Even if the voltage level of the analogue input signal Vin is a constant, a different sensitivity, namely a different voltage resolution of each pulse position numerizing unit 120 causes different output values DT1 to DTm from those units 120. This can perform the A/D conversion with a high preciously.
That is, the pulse position numerizing units 120 in the A/D conversion device 500 have different sampling times, and the adjacent those units 120 have the different sampling times that are shifted by unit time ΔT with one another. Each pulse position numerizing unit 120 performs the A/D conversion from the analogue input signal Vin to the numerical data DTi (i=1 to m) and as a result, provides the numerical data DTi that is shifted by Vd/m, where reference character Vd designates a voltage per LSB (Least Significant Bit) of the numerical data DTi, as shown in FIG. 7A.
The adder 14 receives and adds those numerical data items DTi (i=1 to m) transferred from each of the pulse position numerizing units 120, and outputs numerical data DTA. As shown in FIG. 7B, the numerical data DTA, namely the output data DTA of the adder 14 has the characteristic to increase the level of the output data DTA by one LSB every increment Vd/m of the signal level of the analogue input signal Vin.
That is, the numerical data DTA obtained by adding the numerical data DT1 to DTm has a voltage resolution and a dynamic range of m-times when compared with those of the numerical data DTi before the addition. In other words, the voltage resolution is increased by the number of bits (log2m) increased by the addition, so that the A/D conversion for the analogue input signal Vin can be performed with a high precision.
However, as shown in FIG. 5B, the A/D conversion device 500 disclosed by the Japanese patent laid open publication number JP 2004-7385 generates the m-sampling clocks CK1 to CKm by delaying the reference clock CK0 using the inverter INV0 of a preceding stage and the inverter INVm of a following stage. Further, in order to shift the phases of the sampling clocks CK1 to CKm by Td/m with one another, following parameters Lp, Ln, Wp, and Wn are adjusted:
Gate lengths Lp and Ln; and Transistor widths Wp and Wn, in a P channel transistor and a N channel transistor (such as FET: field effect transistor) forming each inverter INV1 to INVm of following stages.
That is, the delay time corresponding to the phase difference of the sampling clock CK1 to CKm is achieved by adjusting the level necessary for the inverting operation of an inverter that is obtained by adjusting the transistor size (determined by the above parameters) of those N and P channel transistors.
However, the above conventional manner of adjusting the amount of delay time of the clock generator 110, namely an analogue manner to adjust the delay time of each inverter INV1 to INVm by changing the transistor size forming the inverter INV1 to INVm causes a drawback or problem that it is difficult to form each transistor of a desired length and thereby difficult to shift the amount of the delay in each inverter INV1 to INVm by ΔT with a high precisely because in general etching error occurs during IC manufacturing. As a result, it becomes difficult to obtain the conversion characteristic of converting an analogue input signal Vin to numerical data DT1 to DTm in each pulse position numerizing unit 120 with a precisely shifted Vd/m and it further occurs variation of the magnitude of one LSB in the numerical data DTA obtained by adding the numerical data DT1 to DTm. This also causes the drawback that it is difficult to obtain highly precise numerical data from the A/D conversion device.